Vedic-Based Squarers with High Performance

Squaring operation represents a vital in various applications involving image processing, rectangular to polar coordinate conversion, and many other applications. For its importance, novel design for 6-bit squarer basing on the Vedic multiplier (VM) is offered this work. The utilizes dedicated 3-bit modules, (3*3) VM, an improved Brent-Kung Carry-Select Adder (IBK-CSLA) with amended of XOR gate perform fast partial-products addition. circuit can readily be expanded larger sizes such as 12-bit 24-bit numbers which are useful squaring mantissa part 32-bit floating-point numbers. paper also offers three architectures 24- bit using pipelining concept used stages. All these circuits designed VHDL implemented by Xilinx ISE13.2 FPGA. synthesis results reveal that 6-bit, 12- bit, introduce eminent outcomes terms delay area when utilizing IBK-CSLA gate. Also, it found present dissimilar area, architecture based modules VM introduces lowest delay.